1. Field of the Invention
The present invention relates to a high-speed counter.
2. Description of the Prior Art
To facilitate a better understanding of the present invention, a description will be given of a binary counter which is most commonly and widely used in the implementation of a logic circuit or similar one in an electronic computer or the like.
A conventional high-speed binary counter includes a synchronous counter formed by D flip-flops, as shown in FIG. 4. The counting operation of this counter starts with presetting therein an initial value according to a count number, followed by count-up operation counter until it detects an overflow. Reference numeral 41 indicates binary counters and 42 initial value registers.
Where a desired count value is between 0 and 2.sup.n+1 -1, (n+1) flip-flops are connected and, in order to cause a digit i-th from the least significant one to perform a synchronous operation, it is necessary to detect the state in which digits less significant than the i-th digit are all 1s. Accordingly, the counting operation of the conventional system needs the AND of n+1 control signals for count-up control of the most significant digit.
A CMOS (complementary MOS) circuit is usually employed for forming a large scale integrated circuit of small power dissipation, but the maximum fan-in limit of the CMOS circuit is as small as 5 or so. The prior art system includes a circuit of a large fan-in, and hence inevitably adopts a multi-stage configuration therefore, leading to the defect that the operating speed of the conventional high-speed counter decreases with an increase in the count value.